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Registers for serial communication

Abstract

Registers for serial communication.

UDRn

The UDRn is a buffer for transmit and receive data. Shares same address.

UDRn
Bit76543210
NameRXB[7:0]
NameTXB[7:0]

When a UDREn flag of UCSRnA is set, we can write data to transmit buffer.

UCSRnA

The UCSRnA(USART Control and Status Register n A) is a register to control serial communication and status.

UCSRnA
Bit76543210
NameRXCnTXCnUDREnFEnDORnUPEnU2XnMPCMn
RXCn(USART Receive Complete)
Set when unread data exists in receive buffer.
TXCn(USART Transmit Complete)
Set when untransmitted data dose not exist in transmit buffer.
UDREn(USART Data Register Empty)
Set when transmit buffer is ready to get data.
FEn(Frame Error)
Set when next character in the receive buffer has a frame error.
DORn(Data OverRun)
Set when detects data overrun. If the receive buffer is full and detect new start bit.
UPEn(USART Parity Error)
Set when next character in the receive buffer has a parity error.。
U2Xn(Double the USART Transmission Speed)
Effective for asynchronous operation mode. If write 1, set baud rate divider from 16 to 8, so transfer rate is doubling.
MPCMn(Multi-processor Communication Mode)
Enables the multi-processor communication mode.

UCSRnB

UCSRnB
Bit76543210
NameRXCIEnTXCIEnUDRIEnRXENnTXENnUCSZn2RXB8nTXB8n
RXCIEn(RX Complete Interrupt Enable n)
Enables interrupt on the RXCn Flag.
TXCIEn(TX Complete Interrupt Enable n)
Enables interrupt on the TXCn Flag.
UDRIEn(USART Data Register Empty Interrupt Enable n)
Enables interrupt on the UDREn Flag.
RXENn(Receiver Enable n)
Enables the USART Receiver.
TXENn(Transmitter Enable n)
Enables the USART Transmitter.
UCSZn2(Character Size n), UCSZn1 and UCSZn0
Sets the number of data bits
RXB8n(Receive Data Bit 8 n)
The ninth data bit of the received character when 9 bit mode.
TXB8n(Transmit Data Bit 8 n)
The ninth data bit of the transmitting character when 9 bit mode.

UCSRnC

The UCSRnC(USART Control and Status Register n C) is a register for parity, stop bit and so on.

UCSRnC
Bit76543210
NameUMSELn1UMSELn0UPMn1UPMn0USBSnUCSZn1UCSZn0UCPOLn
UMSELn
Sets the operation mode as below. The default is asynchronous USART.
UMSELn1UMSELn0Mode
00Asynchronous USART
01Synchronous USART
10Reserved
11Master SPI
UPMn
Enables and sets type of parity generation and check. The default is disabled.
UPMn1UPMn0Parity Mode
00Disabled
01Reserved
10Enabled, Even Parity
11Enabled, Odd Parity
USBSn
Selects the number of stop bits to be inserted by the transmitter. 1 bit when 0, 2 bit when 1. The default is 1 bit.
UCSZn2, UCSZn1, UCSZn0
Sets the length of data bit. The default is 8 bit.
UCSZn2UCSXn1UCSZn0length
0005 bit
0016 bit
0107 bit
0118 bit
100Reserved
101Reserved
110Reserved
1119 bit
UCPOLn
Sets the relationship between data output change and data input sample, and the synchronous clock (XCKn).

UBRRnL, UBRRnH

Sets the baud rate.

UBRRnL, UBRRnH
Bit76543210
UBRRnH----UBRRn[11:8]
UBRRnLUBRRn[7:0:

12 bit of the 16 bit is valid. The communication speed is calculated as below. The F_CPU is a system clock.

U2Xn = 0
BAUD = F_CPU / (16 (UBRRn + 1))
UBRRn = (F_CPU / (16 * BAUD)) - 1
U2Xn = 1
BAUD = F_CPU / 8 (UBRRn + 1)
UBRRn = (F_CPU / (8 * BAUD)) - 1

Version

Arduino 1.8.13

Last Update

June 19, 2020

inserted by FC2 system