size_tHardwareSerial::write(uint8_tc){_written=true;// If the buffer and the data register is empty, just write the byte
// to the data register and be done. This shortcut helps
// significantly improve the effective datarate at high (>
// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
if(_tx_buffer_head==_tx_buffer_tail&&bit_is_set(*_ucsra,UDRE0)){// If TXC is cleared before writing UDR and the previous byte
// completes before writing to UDR, TXC will be set but a byte
// is still being transmitted causing flush() to return too soon.
// So writing UDR must happen first.
// Writing UDR and clearing TC must be done atomically, otherwise
// interrupts might delay the TXC clear so the byte written to UDR
// is transmitted (setting TXC) before clearing TXC. Then TXC will
// be cleared when no bytes are left, causing flush() to hang
ATOMIC_BLOCK(ATOMIC_RESTORESTATE){*_udr=c;*_ucsra=((*_ucsra)&((1<<U2X0)|(1<<MPCM0)))|(1<<TXC0);}return1;}tx_buffer_index_ti=(_tx_buffer_head+1)%SERIAL_TX_BUFFER_SIZE;// If the output buffer is full, there's nothing for it other than to
// wait for the interrupt handler to empty it a bit
while(i==_tx_buffer_tail){if(bit_is_clear(SREG,SREG_I)){// Interrupts are disabled, so we'll have to poll the data
// register empty flag ourselves. If it is set, pretend an
// interrupt has happened and call the handler to free up
// space for us.
if(bit_is_set(*_ucsra,UDRE0))_tx_udr_empty_irq();}else{// nop, the interrupt handler will free up space for us
}}_tx_buffer[_tx_buffer_head]=c;// make atomic to prevent execution of ISR between setting the
// head pointer and setting the interrupt flag resulting in buffer
// retransmission
ATOMIC_BLOCK(ATOMIC_RESTORESTATE){_tx_buffer_head=i;sbi(*_ucsrb,UDRIE0);}return1;}
// If the buffer and the data register is empty, just write the byte
// to the data register and be done. This shortcut helps
// significantly improve the effective datarate at high (>
// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
if(_tx_buffer_head==_tx_buffer_tail&&bit_is_set(*_ucsra,UDRE0)){// If TXC is cleared before writing UDR and the previous byte
// completes before writing to UDR, TXC will be set but a byte
// is still being transmitted causing flush() to return too soon.
// So writing UDR must happen first.
// Writing UDR and clearing TC must be done atomically, otherwise
// interrupts might delay the TXC clear so the byte written to UDR
// is transmitted (setting TXC) before clearing TXC. Then TXC will
// be cleared when no bytes are left, causing flush() to hang
ATOMIC_BLOCK(ATOMIC_RESTORESTATE){*_udr=c;*_ucsra=((*_ucsra)&((1<<U2X0)|(1<<MPCM0)))|(1<<TXC0);}return1;}
if(bit_is_clear(SREG,SREG_I)){// Interrupts are disabled, so we'll have to poll the data
// register empty flag ourselves. If it is set, pretend an
// interrupt has happened and call the handler to free up
// space for us.
if(bit_is_set(*_ucsra,UDRE0))_tx_udr_empty_irq();}else{// nop, the interrupt handler will free up space for us
}}
_tx_buffer[_tx_buffer_head]=c;// make atomic to prevent execution of ISR between setting the
// head pointer and setting the interrupt flag resulting in buffer
// retransmission
ATOMIC_BLOCK(ATOMIC_RESTORESTATE){_tx_buffer_head=i;sbi(*_ucsrb,UDRIE0);}return1;}