/*
* Print last reset reason of ESP32
* =================================
*
* Use either of the methods print_reset_reason
* or verbose_print_reset_reason to display the
* cause for the last reset of this device.
*
* Public Domain License.
*
* Author:
* Evandro Luis Copercini - 2017
*/#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
#include"esp32/rom/rtc.h"#elif CONFIG_IDF_TARGET_ESP32S2
#include"esp32s2/rom/rtc.h"#elif CONFIG_IDF_TARGET_ESP32C3
#include"esp32c3/rom/rtc.h"#elif CONFIG_IDF_TARGET_ESP32S3
#include"esp32s3/rom/rtc.h"#else
#error Target CONFIG_IDF_TARGET is not supported
#endif
#else // ESP32 Before IDF 4.0
#include"rom/rtc.h"#endif
#define uS_TO_S_FACTOR 1000000 /* Conversion factor for micro seconds to seconds */
voidprint_reset_reason(intreason){switch(reason){case1:Serial.println("POWERON_RESET");break;/**<1, Vbat power on reset*/case3:Serial.println("SW_RESET");break;/**<3, Software reset digital core*/case4:Serial.println("OWDT_RESET");break;/**<4, Legacy watch dog reset digital core*/case5:Serial.println("DEEPSLEEP_RESET");break;/**<5, Deep Sleep reset digital core*/case6:Serial.println("SDIO_RESET");break;/**<6, Reset by SLC module, reset digital core*/case7:Serial.println("TG0WDT_SYS_RESET");break;/**<7, Timer Group0 Watch dog reset digital core*/case8:Serial.println("TG1WDT_SYS_RESET");break;/**<8, Timer Group1 Watch dog reset digital core*/case9:Serial.println("RTCWDT_SYS_RESET");break;/**<9, RTC Watch dog Reset digital core*/case10:Serial.println("INTRUSION_RESET");break;/**<10, Instrusion tested to reset CPU*/case11:Serial.println("TGWDT_CPU_RESET");break;/**<11, Time Group reset CPU*/case12:Serial.println("SW_CPU_RESET");break;/**<12, Software reset CPU*/case13:Serial.println("RTCWDT_CPU_RESET");break;/**<13, RTC Watch dog Reset CPU*/case14:Serial.println("EXT_CPU_RESET");break;/**<14, for APP CPU, reseted by PRO CPU*/case15:Serial.println("RTCWDT_BROWN_OUT_RESET");break;/**<15, Reset when the vdd voltage is not stable*/case16:Serial.println("RTCWDT_RTC_RESET");break;/**<16, RTC Watch dog reset digital core and rtc module*/default:Serial.println("NO_MEAN");}}voidverbose_print_reset_reason(intreason){switch(reason){case1:Serial.println("Vbat power on reset");break;case3:Serial.println("Software reset digital core");break;case4:Serial.println("Legacy watch dog reset digital core");break;case5:Serial.println("Deep Sleep reset digital core");break;case6:Serial.println("Reset by SLC module, reset digital core");break;case7:Serial.println("Timer Group0 Watch dog reset digital core");break;case8:Serial.println("Timer Group1 Watch dog reset digital core");break;case9:Serial.println("RTC Watch dog Reset digital core");break;case10:Serial.println("Instrusion tested to reset CPU");break;case11:Serial.println("Time Group reset CPU");break;case12:Serial.println("Software reset CPU");break;case13:Serial.println("RTC Watch dog Reset CPU");break;case14:Serial.println("for APP CPU, reseted by PRO CPU");break;case15:Serial.println("Reset when the vdd voltage is not stable");break;case16:Serial.println("RTC Watch dog reset digital core and rtc module");break;default:Serial.println("NO_MEAN");}}
voidsetup(){// put your setup code here, to run once:
Serial.begin(115200);delay(2000);Serial.println("CPU0 reset reason:");print_reset_reason(rtc_get_reset_reason(0));verbose_print_reset_reason(rtc_get_reset_reason(0));Serial.println("CPU1 reset reason:");print_reset_reason(rtc_get_reset_reason(1));verbose_print_reset_reason(rtc_get_reset_reason(1));// Set ESP32 to go to deep sleep to see a variation
// in the reset reason. Device will sleep for 5 seconds.
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH,ESP_PD_OPTION_OFF);Serial.println("Going to sleep");esp_deep_sleep(5*uS_TO_S_FACTOR);}