voidHardwareSerial::flush(){// If we have never written a byte, no need to flush. This special
// case is needed since there is no way to force the TXC (transmit
// complete) bit to 1 during initialization
if(!_written)return;while(bit_is_set(*_ucsrb,UDRIE0)||bit_is_clear(*_ucsra,TXC0)){if(bit_is_clear(SREG,SREG_I)&&bit_is_set(*_ucsrb,UDRIE0))// Interrupts are globally disabled, but the DR empty
// interrupt should be enabled, so poll the DR empty flag to
// prevent deadlock
if(bit_is_set(*_ucsra,UDRE0))_tx_udr_empty_irq();}// If we get here, nothing is queued anymore (DRIE is disabled) and
// the hardware finished transmission (TXC is set).
}
// If we have never written a byte, no need to flush. This special
// case is needed since there is no way to force the TXC (transmit
// complete) bit to 1 during initialization
if(!_written)return;
while(bit_is_set(*_ucsrb,UDRIE0)||bit_is_clear(*_ucsra,TXC0)){if(bit_is_clear(SREG,SREG_I)&&bit_is_set(*_ucsrb,UDRIE0))// Interrupts are globally disabled, but the DR empty
// interrupt should be enabled, so poll the DR empty flag to
// prevent deadlock
if(bit_is_set(*_ucsra,UDRE0))_tx_udr_empty_irq();}// If we get here, nothing is queued anymore (DRIE is disabled) and
// the hardware finished transmission (TXC is set).
}